Errors due to parasitic signal propagation adversely affect operation of semiconductor devices, as well as device testing.
An example of this problem may be observed during scattering parameter (abbreviated S-parameter) measurements on bipolar transistors using the Common-Emitter (CE) configuration. S-parameter measurements are common practice and are used extensively to characterize the high-frequency performance of transistors. The CE configuration is preferred for characterizing bipolar transistors used for circuit applications because it is the closest to the configuration used in most digital circuits. Other configurations such as Common-Collector measurements are not sensitive to all capacitances loading the device under test (e.g., collector-to-substrate capacitance). For a discussion of S-parameters see "Application Note 154: S-Parameter Design," Hewlett Packard, April, 1972, pp. 1-22; and "Microwave Theory and Applications," Stephen F. Adam, Prentice-Hall, Inc., Englewood Cliffs, N.J., 1969, pp. 86-89.
A 2-port network is used for CE S-parameter measurements. These two ports are called signal ports 1 and 2, and share a common ground connection. Signal ports 1 and 2 comprise rectangular shaped signal probe pads that are typically 70.times.70 or 100.times.100 .mu.m.sup.2. The port 1 and port 2 signal probe pads are connected by conductive fingers to the base and collector regions of the transistor (i.e., the device under test), respectively. The emitter region is grounded for the measurements, and thus provides the common ground for ports 1 and 2. Using the 2-port network approach has its disadvantages because parasitic signals can propagate through the substrate between ports 1 and 2 during S-parameter measurements of devices built on silicon (Si) substrates.
Parasitic signal propagation produces resonances observed in the vicinity of 1-2 GHz for a reflection measurement on either an "open" calibration structure or on a transistor. These resonances are not corrected by conventional calibration procedures, and thus lead to significant errors in the extraction of S-parameters, particularly for high-gain, high-frequency devices.
Another effect of the parasitic signal propagation is the parasitic transmission between ports 1 and 2. Some calibration procedures do not correct for this error, while others correct for it but still leave some residual error. These errors are inversely proportional to the size of the transistor and proportional to the size of the signal probe pads.
The errors discussed above, particularly parasitic transmission, also affect the performance of transistors during normal operation.
The ground planes typically used today for applications such as analog circuits are the silicon substrates under the active region on the surface on which the transistors/circuits are located. The ground plane is then contacted with a back-side contact.
In complex circuits with many interconnected transistors, a ground plane can eliminate resonances causing signal attenuation or non-linearity (critical for analog applications), and in more general terms, reduce electrical noise. This type of extraneous signal propagation occurs via the substrate.
A second path for extraneous signal propagation occurs between the interconnect lines. The use of a ground plane in the silicon allows reduction of cross-talk or noise generation on adjacent interconnect lines: the electric field radiating from a signal lines terminates on the ground plane rather than coupling to an adjacent line. With a complete ground plane, interconnect lines with controlled impedances can also be achieved. This becomes increasingly important as the frequencies at which signals propagate increase leading to enhanced sensitivity of an interconnect line to its surroundings.
Interconnects wired on the first level of metal, i.e., the closest one to the substrate, will be the ones benefiting the most. They may allow, in some cases, elimination of a metal ground plane above the first interconnect level, or elimination of two parallel grounded interconnects on either side of the signal line ensuring reduction of crosstalk.
While the advantages discussed above play a critical role in high-frequency analog circuits, they are becoming significant issues for digital applications operating at very high clock frequencies.
U.S. Pat. No. 4,791,473 to Phy is directed to a plastic semiconductor device package having an internal ground plane which provides an interlead isolation in order to reduce high frequency signal degradation within the package. A drawback of the Phy plastic package, as well as other conventional techniques such as grounded interconnects, is that such structures require additional manufacturing steps above and beyond those required to produce the semiconductor chip itself.
What is desired is an on-chip ground plane for semiconductor devices that reduces parasitic signals during device operation, and can be manufactured without additional manufacturing steps or cost to the fabrication of the chip itself.